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cy7c1380d cy7c1380f cy7c1382d 18-mbit (512 k 36/1 m 18) pipelined sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05543 rev. *n revised april 23, 2013 18-mbit (512 k 36/1 m 18) pipelined sram features supports bus operation up to 250 mhz available speed grades are 250, 200, and 167 mhz registered inputs and outputs for pipelined operation 3.3 v core power supply 2.5 v or 3.3 v i/o power supply fast clock-to-output times ? 2.6 ns (for 250 mhz device) provides high performance 3-1-1-1 access rate user selectable burst counter supporting intel ? ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed write asynchronous output enable single cycle chip deselect cy7c1380d/cy7c1382d is available in jedec-standard pb-free 100-pin tqfp package; cy7c1380f is available in non pb-free 165-ball fbga package ieee 1149.1 jtag-compatible boundary scan zz sleep mode option functional description the cy7c1380d/cy7c1380f/cy7c1382d sram integrates 524,288 36 and 1,048,576 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive edge triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as they are controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. this part supports byte write operations (see pin definitions on page 6 and truth table on page 9 for further details). write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1380d/cy7c1380f/cy7c1382d operates from a +3.3 v core power supply while all outputs operate with a +2.5 or +3.3 v power supply. all inputs and outputs are jedec-standard and jesd8-5-compatible. selection guide description 250 mhz 200 mhz 167 mhz unit maximum access time 2.6 3.0 3.4 ns maximum operating current 350 300 275 ma maximum cmos standby current 70 70 70 ma
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 2 of 37 logic block diagram ? cy7c1380d/cy7c1380f address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver logic block diagra cyc132d a0, a1, a address register adv clk burst counter and logic q1 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense memory array 2 ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output input dq a, dqp a write driver output buffers dq b, dqp b write driver zz sleep control
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 3 of 37 contents pin configurations ........................................................... 4 pin definitions .................................................................. 6 functional overview ........................................................ 7 single read accesses ................................................ 7 single write accesses initia ted by adsp ................... 7 single write accesses initiate d by adsc ................... 8 burst sequences ......................................................... 8 sleep mode ................................................................. 8 interleaved burst address tabl e ................................. 8 linear burst address table ......................................... 8 zz mode electrical characteri stics .............................. 8 truth table ........................................................................ 9 truth table for read/write ............................................ 10 truth table for read/write ............................................ 10 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 11 disabling the jtag feature ...................................... 11 test access port (tap) ............................................. 11 performing a tap r eset .......... .............. .......... 11 tap registers ...................................................... 11 tap instruction set ................................................... 11 reserved ................................................................... 12 tap controller state diagram ....................................... 13 tap controller block diagram ...................................... 14 tap timing ...................................................................... 15 tap ac switching characteristics ............................... 15 3.3 v tap ac test conditions ....................................... 16 3.3 v tap ac output load equivalent ......................... 16 2.5 v tap ac test conditions ....................................... 16 2.5 v tap ac output load equivalent ......................... 16 tap dc electrical characteristics and operating conditions ............................................. 16 identification register definitions ................................ 17 scan register sizes ....................................................... 17 identification codes ....................................................... 17 boundary scan order .................................................... 18 maximum ratings ........................................................... 19 operating range ............................................................. 19 electrical characteristics ............................................... 19 capacitance .................................................................... 20 thermal resistance ........................................................ 20 ac test loads and waveforms ..................................... 21 switching characteristics .............................................. 22 switching waveforms .................................................... 23 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package diagrams .......................................................... 28 acronyms ........................................................................ 30 document conventions ................................................. 30 units of measure ....................................................... 30 appendix: silicon er rata document for ram9 (90-nm), 18-mb (cy7c138*d) synchronous & nobl? srams ................................... 31 part numbers affected .............................................. 31 product status ........................................................... 31 ram9 sync/nobl zz pin, jtag & chip enable issues er rata summary .................. 31 document history page ................................................. 34 sales, solutions, and legal information ...................... 37 worldwide sales and design s upport ......... .............. 37 products .................................................................... 37 psoc solutions ......................................................... 37
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 4 of 37 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout (3-chip enable) cy7c1380d (512 k 36) cy7c1382d (1 m 18)
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 5 of 37 figure 2. 165-ball fbga (13 15 1.4 mm) pinout (3-chip enable) cy7c1380f (512 k 36) pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/36m nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 6 of 37 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1:a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d input- synchronous byte write select inputs, active low. qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are writt en, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or dese lect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted hi gh, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging fr om a deselected state. adv input- synchronous advance input signal, sampled on th e rising edge of clk, active low . when asserted, it automatically increments t he address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz sleep input . this active high input places the device in a non-time critical sleep condition with data integrity preserved. for normal operati on, this pin has to be low or left floating. zz pin has an internal pull down. dqs, dqp x i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input-static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 7 of 37 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. maximum access delay from the clock rise (t co ) is 2.6 ns (250 mhz device). cy7c1380d/cy7c1380f/cy7c1382d supports secondary cache in systems using a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence suits processors that use a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller addre ss strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burs t counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplif ied with on-chip synchronous self-timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is enabled to propagate to the input of the output registers. at the rising edge of the next clock, the data is enabled to propagate through th e output register and onto the data bus within 2.6 ns (250 mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state; it s outputs are always tri-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output tri-states immediately. single write accesses initiated by adsp this access is initiated when both the following conditions are satisfied at clock rise: (1) adsp is asserted low and (2) ce 1 , ce 2 , and ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dqs inputs is written into the corresponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw x signals. cy7c1380d/cy7c1380f/cy7c1382d provides byte write capability that is described in th e write cycle descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, selectively writes to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. cy7c1380d/cy7c1380f/cy7c1382d is a common i/o device, the output enable (oe ) must be deserted high before presenting data to the dqs inputs. doing so tri-states the output drivers. as a safety precaution, dqs are automatically tri-stated whenever a write cycle is detected, regardless of the state of oe . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin must be disconnecte d. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to the jtag circuitry . if the jtag feature is not being ut ilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . 36m, 72m, 144m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 8 of 37 single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deserted high, (3) ce 1 , ce 2 , and ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is co nducted, only the selected bytes are written. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. cy7c1380d/cy7c1380f/cy7c1382d is a common i/o device, the output enable (oe ) must be deserted high before presenting data to the dqs inputs. doing so tri-states the output drivers. as a safety precaution, dqs are automatically tri-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences cy7c1380d/cy7c1380f/cy7c1382d provides a two-bit wraparound counter, fed by a1:a0, that implements an interleaved or a linear burst sequence. the interleaved burst sequence is designed specifica lly to support intel pentium applications. the linear burst sequence is designed to support processors that follow a lin ear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise auto matically increments the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conserva tion sleep mode. two clock cycles are required to enter into or exit from this sleep mode. while in this mode, data integrity is guaranteed. accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the sleep mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 80 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current t his parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ? ns
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 9 of 37 truth table the truth table for cy7c1380d/cy7c1380f/cy7c1382d follows. [1, 2, 3, 4, 5] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l?h tri-state deselect cycle, power down none l l x l l x x x x l?h tri-state deselect cycle, power down none l x h l l x x x x l?h tri-state deselect cycle, power down none l l x l h l x x x l?h tri-state deselect cycle, power down none l x h l h l x x x l?h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 1. x = don't care, h = logic high, l = logic low. 2. write = l when any one or more byte write enable signals, and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 5. oe is asynchronous and is not sampled with t he clock rise. it is masked internally duri ng write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and a ll data bits behave as output when oe is active (low) .
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 10 of 37 truth table for read/write the truth table for read/write for cy7c1380d/cy7c1380f follows. [6, 7] function (cy7c1380d/cy7c1380f) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes h l l l l l write all bytes l x x x x x truth table for read/write the truth table for read/write for cy7c1382d follows. [6, 7] function (cy7c1382d) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x notes 6. x = don't care, h = logic high, l = logic low. 7. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write is done based on which byte write is active.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 11 of 37 ieee 1149.1 serial boundary scan (jtag) the cy7c1380f incorporates a serial boundary scan test access port (tap).this part is fully compliant with 1149.1. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. cy7c1380f contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state which does not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram on page 13 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see identification codes on page 17 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected betwe en the tdi and tdo balls and enable data to be scanned in and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 14 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this enables data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 18 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identification register definitions on page 17 . tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in identification codes on page 17 . three of these instru ctions are listed as reserved and must not be used. the other five instructions are described in detail in this section. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 12 of 37 the instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest the extest instruction enables the preloaded data to be driven out through the system output pins . this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. idcode the idcode instruction causes a vendor-specific 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. the sample z command places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. the tap controller clock can on ly operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. as there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output undergoes a transi tion. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck# captur ed in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload enables an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data is shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #89 (for 165-ball fbga package). wh en this scan cell, called the ?extest output bus tri-st ate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the outp ut (q-bus) pins, when the extest is entered as the current instru ction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is power ed up, and also when the tap controller is in the te st-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 13 of 37 tap controller state diagram the 0 or 1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 14 of 37 tap controller block diagram bypass register 0 instruction register 0 1 2 identi?cation register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck tms tap controller tdi tdo
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 15 of 37 tap timing figure 3. tap timing t tl test clock (tck) test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined tap ac switchi ng characteristics over the operating range parameter [8, 9] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 8. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 9. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 16 of 37 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 3.3 v tap ac out put load equivalent 2.5 v tap ac test conditions input pulse levels ............ ................................... v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 2.5 v tap ac output load equivalent tdo 1.5v 20pf z = 50 o 50 tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 3.3 v 0.165 v unless otherwise noted) parameter [10] description test conditions min max unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma, v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 10. all voltages referenced to v ss (gnd).
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 17 of 37 identification regi ster definitions instruction field cy7c1380f (512 k 36) description revision number (31:29) 000 describes the version number. device depth (28:24) [11] 01011 reserved for internal use. device width (23:18) 165-ball fbga 000000 defi nes the memory type and architecture. cypress device id (17:12) 100101 defines the width and density. cypress jedec id code (11:1) 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. scan register sizes register name bit size ( 36) instruction 3 bypass 1 id 32 boundary scan order (165-ball fbga package) 89 identification codes instruction code description extest 000 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram outputs to high z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use. this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use. this instruct ion is reserved for future use. reserved 110 do not use. this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. note 11. bit #24 is 1 in the register definitions for both 2.5 v and 3.3 v versions of this device.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 18 of 37 boundary scan order 165-ball bga [12, 13] bit # ball id bit # ball id bit # ball id 1n6 31d10 61g1 2n7 32c11 62d2 3 n10 33 a11 63 e2 4p11 34b11 64f2 5 p8 35 a10 65 g2 6 r8 36 b10 66 h1 7r9 37a9 67h3 8p9 38b9 68j1 9 p10 39 c10 69 k1 10 r10 40 a8 70 l1 11 r11 41 b8 71 m1 12 h11 42 a7 72 j2 13n11 43b7 73k2 14 m11 44 b6 74 l2 15 l11 45 a6 75 m2 16 k11 46 b5 76 n1 17 j11 47 a5 77 n2 18m10 48a4 78p1 19 l10 49 b4 79 r1 20 k10 50 b3 80 r2 21j10 51a3 81p3 22 h9 52 a2 82 r3 23h10 53b2 83p2 24g11 54c2 84r4 25f11 55b1 85p4 26 e11 56 a1 86 n5 27 d11 57 c1 87 p6 28g10 58d1 88r6 29 f10 59 e1 89 internal 30 e10 60 f1 note 12. balls which are nc (no connect) are pre-set low. 13. bit# 89 is pre-set high.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 19 of 37 maximum ratings exceeding the maximum ratings may impair the useful life of the device. for user guidelines, not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .....?0.3 v to +4.6 v supply voltage on v ddq relative to gnd .... ?0.3 v to +v dd dc voltage applied to outputs in tri-state ..........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................ ?0.5 v to v dd + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (per mil-std-883, method 3015) .............. ............ > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [14, 15] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [14] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [14] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd 5 ? a input current of zz input = v ss ?5 ? ? a input = v dd 30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ?350ma 5.0-ns cycle, 200 mhz ?300ma 6.0-ns cycle, 167 mhz ?275ma i sb1 automatic ce power down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ?160ma 5.0-ns cycle, 200 mhz ?150ma 6.0-ns cycle, 167 mhz ?140ma notes 14. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 15. tpower up: assumes a linear ramp from 0 v to v dd(min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 20 of 37 i sb2 automatic ce power down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 70 ma i sb3 automatic ce power down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ?135ma 5.0-ns cycle, 200 mhz ?130ma 6.0-ns cycle, 167 mhz ?125ma i sb4 automatic ce power down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 80 ma electrical characteristics (continued) over the operating range parameter [14, 15] description test conditions min max unit capacitance parameter [16] description test conditions 100-pin tqfp package 165-ball fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 59pf c clk clock input capacitance 5 9 pf c io input/output capacitance 5 9 pf thermal resistance parameter [16] description test conditions 100-pin tqfp package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.66 20.7 c/w ? jc thermal resistance (junction to case) 4.08 4.0 c/w note 16. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 21 of 37 ac test loads and waveforms figure 4. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 22 of 37 switching characteristics over the operating range parameter [17, 18] description 250 mhz 200 mhz 167 mhz unit min max min max min max t power v dd (typical) to the first access [19] 1 ?1?1? ms clock t cyc clock cycle time 4.0 ?5?6? ns t ch clock high 1.7 ?2.0?2.2? ns t cl clock low 1.7 ?2.0?2.2? ns output times t co data output valid after clk rise ? 2.6?3.0?3.4 ns t doh data output hold after clk rise 1.0 ?1.3?1.3? ns t clz clock to low-z [20, 21, 22] 1.0 ?1.3?1.3? ns t chz clock to high-z [20, 21, 22] ? 2.6?3.0?3.4 ns t oev oe low to output valid ? 2.6?3.0?3.4 ns t oelz oe low to output low-z [20, 21, 22] 0 ?0?0? ns t oehz oe high to output high-z [20, 21, 22] ? 2.6?3.0?3.4 ns setup times t as address setup before clk rise 1.2 ?1.4?1.5? ns t ads adsc , adsp setup before clk rise 1.2 ?1.4?1.5? ns t advs adv setup before clk rise 1.2 ?1.4?1.5? ns t wes gw , bwe , bw x setup before clk rise 1.2 ?1.4?1.5? ns t ds data input setup before clk rise 1.2 ?1.4?1.5? ns t ces chip enable setup before clk rise 1.2 ?1.4?1.5? ns hold times t ah address hold after clk rise 0.3 ?0.4?0.5? ns t adh adsp , adsc hold after clk rise 0.3 ?0.4?0.5? ns t advh adv hold after clk rise 0.3 ?0.4?0.5? ns t weh gw , bwe , bw x hold after clk rise 0.3 ?0.4?0.5? ns t dh data input hold after clk rise 0.3 ?0.4?0.5? ns t ceh chip enable hold after clk rise 0.3 ?0.4?0.5? ns notes 17. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 18. test conditions shown in (a) of figure 4 on page 21 unless otherwise noted. 19. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 20. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 4 on page 21 . transition is measured 200 mv from steady-state voltage. 21. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bu s contention condition, but reflect paramete rs guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 22. this parameter is sampled and not 100% tested.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 23 of 37 switching waveforms figure 5. read cycle timing [23] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx data out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address dont care undefined note 23. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 24 of 37 figure 6. write cycle timing [24, 25] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for ?rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined notes 24. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 25. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low .
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 25 of 37 figure 7. read/write cycle timing [26, 27, 28] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw x data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 dont care undefined a3 notes 26. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 27. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 28. gw is high.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 26 of 37 figure 8. zz mode timing [29, 30] switching waveforms (continued) t zz i supply clk zz t zzrec all inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 29. device must be deselected when entering zz mode. see truth table on page 9 for all possible signal conditions to deselect the device. 30. dqs are in high z when exiting zz sleep mode.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 27 of 37 ordering information the below table lists the key package features and ordering codes. the table contains only the pa rts that are currently availab le. if you do not see what you are looking for, contact your local sa les representative. for more information, visit the cypress websi te at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions speed (mhz) ordering code package diagram part and package type operating range 250 CY7C1380D-250AXC 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial 200 cy7c1380d-200axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1382d-200axc 167 cy7c1380d-167axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1382d-167axc cy7c1380d-167axi 51-85050 100-pin tqfp (14 20 1. 4 mm) pb-free industrial cy7c1380f-167bzi 51-85180 165-ball fbga (13 15 1.4 mm) temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bz a = 100-pin tqfp bz = 165-ball fpbga frequency range: xxx = 250 mhz or 200 mhz or 167 mhz die revision: x = d or f d ? 90 nm f ? 90nm errata fix pcn084636 part identifier: 138x = 1380 or 1382 1380 = scd, 512 k 36 (18 mb) 1382 = scd, 1 mb 18 (18 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 138x x - xxx x xx x c
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 28 of 37 package diagrams figure 9. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 29 of 37 figure 10. 165-ball fbga (13 15 1.4 mm) bb165d /bw165d (0.5 ball diameter) package outline, 51-85180 package diagrams (continued) 51-85180 *f
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 30 of 37 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jtag joint test action group lsb least significant bit msb most significant bit oe output enable sram static random access memory tck test clock tms test mode select tdi test data-in tdo test data-out tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 31 of 37 appendix: silicon errata do cument for ram9 (90-nm), 18- mb (cy7c138*d) synchronous & nobl? srams this section describes the ram9 sync/nobl zz pin, jtag and ch ip enable issues. details include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. please contact your local cypress sales representative if you have further questions. part numbers affected product status all of the devices in the ram9 4mb/18mb/72mb sync/nobl family are qualified and available in production quantities. ram9 sync/nobl zz pin, jtag & chip enable issues errata summary the following table defines the errata applicable to available ram9 18mb sync/nobl family devices. density & revision package type operating range 18mb-ram9 synchronous srams: cy7c138*d all packages commercial/ industrial item issues description device fix status 1. zz pin when asserted high, the zz pin places device in a ?sleep? condition with data integrity preserved.the zz pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 18m-ram9 (90nm) for the 18m ram9 (90 nm) devices, there is no plan to fix this issue. 2. jtag functionality during jtag test mode, the boundary scan circuitry does not perform as described in the datasheet.however, it is possible to perform the jtag test with t hese devices in ?bypass mode?. 18m-ram9 (90nm) this issue will be fixed in the new revision, which use the 65 nm technology. please contact your local sales rep for availability. 3. chip enable the internal chip enable ce3# pad is floating instead of being tied to ground. this floating input may cause unstable behavior of the device during normal mode of operation. 18m-ram9 synchronous srams 119-ball bga package option only (90nm) this issue was fixed in the new revision of the device by a substrate change. please contact your local sales rep for availability.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 32 of 37 1. zz pin issue problem definition the problem occurs only when the device is operated in the no rmal mode with zz pin left floating. the zz pin on the sram device does not have an internal pull-do wn resistor. switching noise in the system may cause the sram to recognize a high on the zz input, which may cause the sram to enter sleep mode. this could result in incorrect or undesirable operation of the sram. trigger conditions device operated with zz pin left floating. scope of impact when the zz pin is left floating, the device delivers incorrect data. workaround tie the zz pin externally to ground. fix status fix was done for the 72mb ram9 synchronous srams and 72m ram9 nobl srams devices. fixed devices have a new revision. the following table lists the devices affected and the new revision after the fix. 2. jtag functionality problem definition the problem occurs only when the device is operated in the jt ag test mode.during this mode , the jtag circuitry can perform incorrectly by delivering the incorrect data or the incorrect scan chain length. trigger conditions several conditions can trigger this failure mode. 1. the device can deliver an incorrect lengt h scan chain when operating in jtag mode. 2. some byte write inputs only recognize a logic high level when in jtag mode. 3. incorrect jtag data can be read from the device wh en the zz input is tied high during jtag operation. scope of impact the device fails for jtag tes t. this does not impact the normal functionality of the device. workaround 1.perform jtag testing with t hese devices in ?bypass mode?. 2.do not use jtag test.
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 33 of 37 3. chip enable issue problem definition the die used for cy7c138*d has three chip enables, ce1#, ce2 and ce3#. the devices having part numbers cy7c138*d (with 119-ball bga package option only) utilize a single chip enable (ce1#) signal. ce2 and ce3# signals which are unused should be internally connected to vcc and ground respectively to keep them in ?enabled? state, thus allowing ce1# to have full control of the chip. the internal chip enable ce3# pad is fl oating instead of being tied to ground. this state of ce3# sig nal can result in incorrect or undes irable operation of the sram. trigger conditions there are no specific trigger conditions. the issue can o ccur at any time during the normal operation of the device. scope of impact this issue affects the normal functionality, and can cause unstable oper ation of the device. workaround use the fixed revision of the device. fix status fix was done for all the devices having this issue and was invo lved re-design of the substrate in order to have ce2 and ce3# pads bonded to vcc and ground lines respectively in the substr ate. fixed devices have a new revision. the following table lists the devices affected and the new revision after the fix. table 1. list of affected devices and the new revision revision after the fix new revision after the fix cy7c138*d (119-ball bga package) cy7c138*f (119-ball bga package)
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 34 of 37 document history page document title: cy7c1380d/cy7c1380f/cy7c1382d, 18-mbit (512 k 36/1 m 18) pipelined sram document number: 38-05543 rev. ecn no. submission date orig. of change description of change ** 254515 see ecn rkf new data sheet. *a 288531 see ecn syt updated selection guide (removed 225 mhz and 133 mhz frequencies related information). updated ieee 1149.1 serial boundary scan (jtag) (edited description for non-compliance with 1149.1). updated electrical characteristics (removed 225 mhz and 133 mhz frequencies related information). updated switching characteristics (removed 225 mhz and 133 mhz frequencies related information). updated ordering information (added pb-free information for 100-pin tqfp, 119-ball bga and 165-ball fbga packages) and added comment for ?pb-free bg packages availability? below the ordering information. *b 326078 see ecn pci updated pin configurations (address expansion pins/balls in the pinouts for all packages are modified as per jedec standard). updated ieee 1149.1 serial boundary scan (jtag) (updated tap instruction set (updated overview (description), updated extest (description), added extest output bus tri-state )). updated identification register definitions (splitted device width (23:18) into two rows (one for 119-ball bga and another for 165-ball fbga), retained the same values of 165-ball fbga and changed the values from 000000 to 101000 for 119-ball bga) updated electrical characteristics (modified test conditions for v ol, v oh parameters). updated thermal resistance (changed ? ja and ? jc for 100-pin tqfp package from 31 and 6 ? c/w to 28.66 and 4.08 ? c/w respectively, changed ? ja and ? jc for 119-ball bga package from 45 and 7 ? c/w to 23.8 and 6.2 ? c/w respectively, changed ? ja and ? jc for 165-ball fbga package from 46 and 3 ? c/w to 20.7 and 4.0 ? c/w respectively). updated ordering information (updated part numbers) and removed comment of ?pb-free bg packages availab ility? below the ordering information. *c 416321 see ecn nxr changed status from preliminary to final. changed address of cypress semicondu ctor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (changed the description of i x parameter from input load current to input leakage current, changed the minimum and maximum values of i x parameter (corresponding to input current of mode) from ?5 ? a and 30 ? a to ?30 ? a and 5 ? a, changed the minimum and maximum values of i x parameter (corresponding to input current of zz) from ?30 ? a and 5 ? a to ?5 ? a and 30 ? a, updated note 15 ). updated ordering information (updated part numbers) and replaced package name column with package diagram in the ordering information table. *d 475009 see ecn vkn updated tap ac switching characteristics (changed minimum values of t th , and t tl parameters from 25 ns to 20 ns, and maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added the maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers).
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 35 of 37 *e 776456 see ecn vkn updated features (included cy7c1380f/cy7c1382f related information). updated functional description (included cy7c1380f/cy7c1382f related information). updated logic block diagram ? cy7c1380d/cy7c1380f (included cy7c1380f related information, added the note ?cy7c1380f and cy7c1382f in 119-ball bga package have only 1 chip enable (ce 1 ).? and referred the same note in the title). updated logic block diagram ? cy7c1382d/cy7c1382f (included cy7c1382f related information, added the note ?cy7c1380f and cy7c1382f in 119-ball bga package have only 1 chip enable (ce 1 ).? and referred the same note in the title). updated pin configurations (included cy7c1380f/cy7c1382f related information). updated functional overview (included cy7c1380f/cy7c1382f related information). updated truth table (included cy7c1380f/cy7c1382f related information). updated truth table for read/write (included cy7c1380f related information). updated truth table for read/write (included cy7c1382f related information). updated ieee 1149.1 serial boundary scan (jtag) (included cy7c1380f/cy7c1382f related information). updated identification register definitions (included cy7c1380f/cy7c1382f related information). updated ordering information (updated part numbers). *f 2648065 01/27/09 vkn / pyrs updated ordering information (to include cy7c1380f/cy7c1382f in 100-pin tsop package and 165-ball fbga package) and modified text on top of the ordering information table. *g 2897120 03/22/2010 njy updated ordering information (removed inactive parts). updated package diagrams . *h 3067398 10/20/10 njy updated ordering information (the part cy7c1380f-167bgc is found to be in ?eol-prune? state in oracle plm and therefore, it has been removed) and added ordering code definitions . *i 3159479 02/01/2011 njy added acronyms and units of measure . minor edits and updated in new template. updated package diagrams . *j 3192403 03/10/2011 njy updated in new template. *k 3210400 03/30/11 njy updated ordering information (removed pruned part cy7c1380d-167bzc from the ordering information table). document history page (continued) document title: cy7c1380d/cy7c1380f/cy7c1382d, 18-mbit (512 k 36/1 m 18) pipelined sram document number: 38-05543 rev. ecn no. submission date orig. of change description of change
cy7c1380d cy7c1380f cy7c1382d document number: 38-05543 rev. *n page 36 of 37 *l 3575733 04/09/2012 njy / prit updated features (removed cy7c1382f related information, removed 165-ball fbga package related information for cy7c1382d, removed 100-pin tqfp package related information for cy7c1380f, removed 119-ball bga package related information). updated functional description (removed the note ?for best practices or recommendations, please refer to the cypress application note an1064, sram system design guidelines on www.cypress.com .? and its reference, removed the note ?ce 3, ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in 1 chip enable.? and its reference). updated logic block diagram ? cy7c1380d/cy7c1380f (removed the note ?cy7c1380f and cy7c1382f in 119-ball bga package have only 1 chip enable (ce 1 ).? and its reference). updated logic block diagram ? cy7c1382d (removed cy7c1382f related information, removed the note ?cy7c1380f and cy7c1382f in 119-ball bga package have only 1 chip enable (ce 1 ).? and its reference). updated pin configurations (removed cy7c1382f related information, removed 119-ball bga package related information, removed 100-pin tqfp package related information for cy7c1380f, removed 165-ball fbga package related information for cy7c1382d, removed the note ?ce 3, ce 2 are for 100-pin tqfp and 165-ball fbga packages only. 119-ball bga is offered only in 1 chip enable.? and its reference). updated functional overview (removed cy7c1382f related information). updated truth table (removed cy7c1382f related information). updated truth table for read/write (removed cy7c1382f related information). updated ieee 1149.1 serial boundary scan (jtag) (removed cy7c1380d, cy7c1382d, and cy7c1382f related information). updated identification register definitions (removed cy7c1380d, cy7c1382d, and cy7c1382f related information, removed 119-ball bga package related information). updated scan register sizes (removed 119-ball bga package related information). removed boundary scan order (corresponding to 119-ball bga). updated capacitance (removed 119-ball bga package related information). updated thermal resistance (removed 119-ball bga package related information). updated package diagrams (removed 119-ball bga package related information). *m 3945784 03/27/2013 prit updated package diagrams : spec 51-85180 ? changed revision from *e to *f. *n 3977530 04/23/2013 prit added appendix: silicon errata document for ram9 (90-nm), 18-mb (cy7c138*d) synchronous & nobl? srams . document history page (continued) document title: cy7c1380d/cy7c1380f/cy7c1382d, 18-mbit (512 k 36/1 m 18) pipelined sram document number: 38-05543 rev. ecn no. submission date orig. of change description of change
document number: 38-05543 rev. *n revised april 23, 2013 page 37 of 37 i486 is a trademark, and intel and pentium are registered trademarks of intel corporation. powerpc is a trademark of ibm corpor ation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1380d cy7c1380f cy7c1382d ? cypress semiconductor corporation, 2004-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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